product databrief www.pericom.com | 1-408-435-0800 pi2eqx5904 5.0gbps, 4-lane pcie ? 2.0 redriver tm with equalization and emphasis features ? up to 5.0gbps pcie ? 2.0 serial redriver? ? supporting 8 differential channels or 4 lanes of pcie interface ? pin strapped and i 2 c configuration control (3.3v tolerant i 2 c) ? adjustable reciever equalization ? adjustable transmitter amplitude and de-emphasis ? increased output drive for longer trace and cable applications ? variable input and output termination ? 1:2 channel broadcast ? channel loop-back/mux and demux mode ? low power: 660mw, typical ? electrical idle fully supported ? receiver detect and individual output control ? single supply voltage, 1.2v 0.05v ? power down modes ? industrial temp support, -40c ~ +85c ? packaging (pb-free & green): 100-contact lbga pericom semiconductors pi2eqx5904 (or 5964) is a low power, pcie ? compliant signal redriver also suitable for other high speed serial signals such as serdes backplane and non protocol specific protocols. the device provides programmable equalization, amplification, and de-emphasis by using 8 select bits to optimize performance over a variety of physical mediums by reducing inter-signal interference. pi2eqx 5904 supports eight 100 w differential cml data i/os between the protocol asic to a switch fabric, across a backplane, or extends the signal across other distant data pathways on the user platform. pi2eqx5904 compensates signal insertion loss at designated ber issued by pcie2.0 endpoint device. the integrated equalization circuitry provides flexibility with the signal integrity of the pcie signal before the redriver, whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the signal after the redriver. in addition to providing signal re-conditioning, pericoms pi2eqx5904 also provides power management stand-by mode operated by a power down pin. target markets for this redriver are networking, embedded, industrial, server and storage applications, including non- protocol-specific and high-speed signal applications. block diagram + ? + ? + ? + ? + ? + ? a b xytx- xytx+ xyrx+ xyrx- equalizer equalizer input level detec t to control logic output controls output controls input level detec t to control logic data lane repeats 4 t imes control registers & logic power management i 2 c control sel y_x sy_x dy_x de_x pd# sda scl mode lb# res_x rxd_x ax xytx- xytx+ xyrx+ xyrx- redrivers with emphasis and equalization signal conditioning technology ensure the integrity of high-frequency pcie signals by opening closed signal eyes to recover data and meet strict compliance testing requirements. increased signal margin also supports longer drive lenghts over even low-quality cables. pcie 2.0 cable blade server blade server pcie 2.0 redriver figure1 pi3eqx7711 pi3eqx6701
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